A Resistor/Trimming-Less Self-Biased Current Reference Class with Area Down to $3,500\ \mu \mathrm{m}^{2}$, 42.8 pW Power and 10.4% Accuracy across Corner Wafers in 180 nm

Current references are fundamental building blocks in sensor interfaces and other analog circuitries [1]–[9]. In applications with low-cost targets, their area and testing effort need to be minimized, and trimming must be eliminated. In power-constrained systems, their net power (i.e., not going into their output bias current
$I_{REF})$
and minimum supply voltage
$V_{min}$
need to be kept low, so as to minimize the power burden and remove supply scaling limitations at the system level. Unfortunately, lower net power generally leads to poorer accuracy due to PVT variations, requiring innovation to make the power-accuracy tradeoff more favorable while avoiding trimming.