A 80Gb/s/pin Single-Ended PAM-4 Transmitter With an Edge Boosting Auxiliary Driver and a 4-Tap FFE in 28-nm CMOS

The demands for the higher-bandwidth memory access are continuously increasing for many applications such as data centers, HPC, and AI processors. With this, the importance of high-speed memory interfaces is increasing as well and a number of technical approaches are being pursed in order to overcome the channel bandwidth limitation. Especially, the pulse amplitude modulation 4 (PAM-4) technique is actively investigated [1]–[4]. PAM-4 can reduce the symbol rate by half but at the cost of the reduced signal-to-noise ratio (SNR), resulting in the increased bit error rate (BER)[5]. To minimize the SNR decrease, the level-separation mismatch ratio (RLM) should be optimized. Furthermore, the performance of equalizers should be well optimized for inter-symbol interference (ISI) reduction. This article presents the technique of achieving a 80Gb/s transmitter (TX) with a PAM-4 single-ended voltage mode (VM) driver implemented in 28-nm CMOS technology, which includes a reconfigurable 4-tap feed-forward equalizer (FFE) and an edge-boosting auxiliary driver for channel equalization.