A 0.000261 mm2 Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS

The demand for high-performance and area-efficient SAR ADC has been rising over the past years for ADC-based wireline receiver and mixed-signal computing. The small size of the sub-ADC brings better accuracy and throughput in these array-based applications, because the small implementation mitigates the heavy routing and parasitic effects, thereby improving energy efficiency, signal integrity, and speed. A capacitor-array DAC (CDAC)-based SAR ADC [1] is the de-facto standard architecture for these needs, however, the exponential trade-off between resolution and the CDAC size imposes a limitation on the area-efficiency where more compact designs are desired. CDACs with bridge capacitors alleviate this trade-off, however, the gain error between the stages tolls significant complexity for calibration, i.e., needing a high-speed reference driver or a trimming array. The charge-injection DAC (ciDAC) can achieve higher density by exploiting its cascade-ability as it facilitates the gain error calibration through its (zero-load) bias terminal. Furthermore, hybridizing the CDAC and ciDAC synergistically achieves higher performance density (characterized by information rate density or IRD,
$\text{TSps}\cdot \text{conv-steps/mm}^{2}$
[2]) while taming the artifacts of each architecture (e.g., exponential area, limited input range). This paper demonstrates a 3-stage capacitor array-assisted charge-injection DAC-based SAR ADC (c-ciSAR ADC) achieving the highest IRD. The prototype ADC with 1 GS/s 8-bit resolution achieves a state-of-the-art IRD of 470
$\text{TSps}\cdot \text{conv-steps/mm}^{2}$
from a 1 V supply in 28 nm CMOS.