Selected Issues Causing Meta-stability in Digital Circuits and Approaches to Avoiding Them

This paper presents selected issues that may occur in digital circuit design flow. The first problem deals with reset signal. The digital circuits become more robust and their design requires considering the pros and cons of different reset architectures to apply a proper one. The second issue is related to meta-stability, which is frequently caused by either setup time or hold time violations. Closely related with this issue is Clock Domain Crossing (CDC) that happens when the output of a flip-flop is fed to the input of another flip-flop and these flip-flops do not share the same clock domain. The last section offers information about a clock multiplexer or a clock switch.