Compact Modeling of Spintronics Devices for Application-based Circuit-level Simulation

Neural network (NN) has inspired brain-like functionality for various applications. Researchers constantly intend to newer techniques in terms of algorithms, architectures, circuits, and devices for more efficient and reliable NNs. The basic step is to achieve a computing-in-memory (CiM) design for implementing an efficient NN because, inside the brain, computing and memory blocks are not placed separately. Hence, the objective is to overcome the memory and processing bottleneck of conventional von-Neumann architecture. As compared to the charge-based CMOS technology, spintronics utilizes the spin orientation of an electron and its magnetic moment as a state variable. Spintransfer-torque (STT) and spin-orbit torque (SOT) based magnetic random-access memories (MRAMs) are the most reported spintronic memories. Data congestion between processor and memory in computing systems can be avoided using computing-in-memory architectures that can be easily incorporated into the spin devices due to their inherent properties.