Study on the Metal-Graphene Contact Resistance Achieved With One-Dimensional Contact Architecture

Graphene has always been considered as one of the materials with the greatest potential for the realization of improved microelectronic and photonic devices. But to actually reach its full potential in Si CMOS technology, graphene-based devices need to overcome different challenges. They do not only need to have better performances than standard devices, but they also need to be compatible with the production of standard Si based devices. To address the first challenge the main route requires the optimization of the contact resistance, that highly reduces the devices performance, while the second challenges requires the integration of graphene inside the standard production lines used for microelectronic. In this work we used an 8" wafer pilot-line to realize our devices and we studied the behavior of the contact resistance between metal and graphene obtained by one-dimensional contact architecture between the two materials. The contact resistance has been measured by means of Transmission Line Method (TLM) with several contact patterning.