Design of A Picosecond Resolution Control Loop for Fine TDC Based on 0.11 μm CMOS Process

Our group has developed a multi-voltage threshold (MVT) digitizer implemented on the application-specific integrated circuit (MVT ASIC). This new digital converter offers the advantages of low power consumption, high efficiency, and small size. In addition, it also improves the time resolution. To further enhance the performance of the MVT ASIC and silicon photomultiplier (SiPM), we propose to implement the MVT ASIC based on the 0.11 µm CMOS process. Because of the inherent delay limit of ~50 ps in this process, designing a time-to-digital converter (TDC) with 20 ps resolution is a challenge. Therefore, we propose a resolution control loop based on a two-stage phase-locked and vernier delay line structure to overcome this limitation. Through simulation, we have shown that the proposed method can achieve a ~20 ps time resolution based on a 0.11 µm process.