A Deeply Pipelined FMA Unit for High Performance RISC-V Processor

The open RISC-V instruction set architecture provides a new innovative platform for integrated circuit design, and the multiplier and adder are the core units of the computing unit. This paper designs a high-performance 64-bit floating-point multiply-add operation unit based on the RISC-V floating-point instruction set, which supports single-precision, double-precision and half-precision calculations, and can realize a deep pipeline design with a maximum execution stack of 10 levels. In the VIVADO simulation environment, the function verification of the floating-point multiplication and addition unit is carried out, and each module can meet the correctness requirements. The results show that under the 28nm CMOS process, the longest critical path delay is 500ps, the slack is 0.09, and the operating frequency is 1.67GHz.