Life Prediction of the Delaminations of SiP Based on Physics-of-Failure

The development of SiP chips has driven the lightweight trend in electronics, but it also brings new reliability issues, especially package delamination caused by compound stress. This paper proposes a method for predicting the layered lifetime of SiP chip packaging based on physics-of-failure model. Taking an energy SiP module and its key components as an example, this paper analyzes the mechanism and influencing factors of package layering failure in different parts of SiP chip during reflow welding process and use. Through physics-of-failure model, the life of SiP chip in packaging layering process and reflow welding process is predicted. This research is of great significance for identifying weak points in SiP chip and the improvement of the design method.

I. Introduction

SiP chip is a combination of various functional devices from the point of view of system optimization. Its application has greatly promoted the lightweight trend of electronic products. SiP chip has the advantages of high integration, reduced layout and wiring difficulty, and better reliability in anti-electromagnetic interference, but also introduced new reliability problems.