HW/SW implementation of RSA digital signature on a RISC-V-based System-on-Chip

A digital signature is a cryptographic technique used to generate the signature of a message and verify the signature of that particular message. This signature scheme can ensure the validation of the authenticity, integrity, and non-repudiation of a message. Nowadays, the public-key cryptosystem RSA is widely used to perform the digital signature by using a public/private key pair. This paper describes the software and hardware hybrid implementation of the RSA digital signature on a System-on-Chip (SoC) that uses a RISC-V processor as processing core. The key generation for the RSA has been done in software, and the most time-consuming mathematical operation behind the RSA algorithm, the modular exponentiation, has been implemented in hardware. The proposed approach has been validated using one Xilinx Kintex-7 FPGA on the Genesys-2 FPGA board. The acceleration factor has also been calculated by comparing the software versus hardware implementation. The designed RSA IP has the flexibility to be reconfigured with different key sizes (512, 1024, 2048 bits) as per the requirements of the security level. The proposed implementation is verified using the National Institute of Standards and Technology (NIST) test vectors.

I. Introduction

Digitalization has transformed our daily lives but some challenges should be faced to guarantee the security of important services to citizens and industrial sectors. Current Information and Communication Technologies (ICT) systems rely on networked Internet-enabled devices that can communicate with each other and provide connections to remote cloud environments. The security of these devices is usually built over a Root-of-Trust (RoT) that can be implemented following different strategies. A full hardware realization of a RoT that integrates reliable secret keys, entropy source, and cryptographic implementations for data encryption/decryption and digital signatures, introduces several advantages. Firstly, all components of the RoT are attached to a processor core as a System-on-Chip (SoC), that is, the RoT components are physically placed in a single component reducing the security perimeter to one unique chip. This strategy prevents a clear vulnerability of RoT composed of several chips, where one or more elements can be substituted by malicious ones, prone to counterfeiting attacks. A full hardware RoT is also robust against malicious software that can be injected into the Operating Systems (OS) of the processing cores. Furthermore, it offers the best performance in terms of power and timing responses, both are critical factors for Internet-of-Things (IoT) devices with severe restrictions, such as battery life and limited resources on embedded processors.