Optimization in PFSCL Design Using Floating-Gate MOSFET

This work suggests a FGMOS-based efficient exclusive-OR (XOR) gate design for PFSCL. The pull-down transistor is changed to a FGMOS transistor in the proposed design, which eliminates the pull-down transistor threshold voltage and reduces the overall voltage supply demand by a factor of the threshold voltage. The effectiveness of the proposed PFSCL XOR gate design and the already existing triple tail cell-based design were compared. Through a number of SPICE simulations using 45nm PTM CMOS technology parameters, the functionality of both designs was confirmed.