A Modified Low-Offset High Speed Comparator Circuit for Flash Converter Architecture

Advances in the implementation of hand held devices would not be possible without the accurate design of an analog to digital converter architecture. An essential component in this converter architecture is the CMOS comparator. The previous comparators operate with high delay, due to which the speed reduces as well as the circuits suffer from larger offset voltages. In this work, a modified CMOS comparator architecture is developed to study its non-linear and time varying characteristics. The propagation delay, power dissipation, power delay product and offset voltage analysis are carried out in this work and compared with the conventional comparator. The proposed comparator architecture is designed and simulated in Cadence Virtuoso tools in 180nm CMOS process technology at a power supply voltage
$\mathrm{V}_{\text{DD}}=1.8\mathrm{V}$
. Com pared to the earlier comparator architectures, the offset voltage reduced by 9%, power delay product deceased by 12% and the total delay reduced by 8%. Based on the obtained simulation results, the proposed modified comparator circuit can be used in the comparator bank segment of a Flash analog to digital converter architecture.