Review of Performance Analysis of Some Basic Full Adder Circuits

A basic building block of VLSI circuits and systems is a Full Adder (FA) Circuit. A FA circuit is the central digital circuit that performs addition. It is an important component of VLSI circuits and systems. A complete adder circuit can be designed in a variety of ways. The major goal of this is to investigate the performance of some F As such as CMOS, CPL, TGA, and HYBRID circuits. P (Power), D (Delay), PDP (Power Delay Product), and EDP (Energy Delay Product) are the various performance parameters. Performance comparisons are also conducted. It is observed that CMOS is a robust design, CPL is the worst design, TGA has better performance as compared to CMOS and CPL, whereas hybrid FA has the best performance in the gdk 130nm Technology node. Mentor Graphics EDA (Electronic Design Automatic) Tool is used for all simulation.