Improving the thermal ruggedness of GaAs HBTs through nonuniform base ballasting optimization

This paper promotes the adoption of an automatically-determined nonuniform configuration of base ballasting resistors (R
B
s) to extend the safe operating area (SOA) of arrays made of paralleled heterojunction bipolar transistors (HBTs). This strategy mitigates electrothermal (ET) effects compared to the standard approach based on a uniform base ballasting distribution, thus delaying the occurrence of the maximum temperature withstandable by the individual HBTs. The optimum set of R
B
s is calculated through an iterative in-house routine, which makes use of a freeware named TADS interface to connect MATLAB and Keysight ADS. The core of the routine is represented by circuit-based ET simulations in ADS. As a case study, a 14-HBT array in GaAs technology was considered, the optimum R
B
s set of which was efficiently computed in less than 2 minutes. It is shown that the SOA boundary is significantly pushed rightward with respect to the uniform configuration, without price to pay in terms of bandwidth reduction.