A Layout Area Reduction of Basic Logic Element by Using a Neuron CMOS Type 4-input Variable Logic Circuit

As Field Programmable Gate Arrays (FPGAs) become large integration, the area reduction of a Basic Logic Element (BLE), which is a circuit for a logical definition in FPGAs, is required. We have studied a Variable Logic Circuit (vVLC) using neuron CMOS inverters (vCMOSs) and have proposed a 4-input Variable Logic Circuit (4-vVLC) as an alternative circuit against a 4-input Look-Up Table circuit (4-LUT) in the ordinary BLE. In this paper, we describe the 4-vVLC configuration and operations, and verify that the results of the HSPICE simulations and the theoretical performances are in general agreement. In addition, we design a layout of BLEs using 4-vVLC to reduce the BLE area and compare the 4-LUT and 4-vVLC.