A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System

The ternary logic approach was proposed in an asynchronous digital system to eliminate overhead wires for communication signals in preference to the binary logic approach. Spacer detectors (SDs) are crucial in ternary logic to determine whether or not the input voltage is equivalent to empty. The Internet of Things (IoT) devices leverage asynchronous multi-value logic systems for machine learning inference to minimize power consumption. These IoT devices are also expected to operate at ultra-low operating voltages (sub- or near-threshold voltages). An ultra-low supply voltage restricts the operation of the SD circuit because of the need to determine the space value with a logical intermediate value. This study presented SD circuits was applied a pseudodifferential amplifier instead of the traditional element-based inverter circuit to design H-element and L-element. Hence, our proposed SD circuits can operate at low supply voltage without body bias using a bulk-controlled method. The proposed circuit was simulated in 65 nm UMC LL process technology in the Cadence Virtuoso analogue design environment with power consumption compared with the difference in supply voltage from 0.35 to 0.9 volts.