An Assessment of Sample Preparation Challenges in 3D Stacked Integrated Circuit Devices for Post-Silicon Verification and Validation

This paper presents an investigation into the challenges of sample preparation and large-area delayering of a 3D stacked integrated circuit (IC) for post-silicon IC verification and validation (V&V). In this study, a commercial-off-the-shelf (COTS) device was depackaged and deprocessed to better understand the limitations of conventional sample preparation workflows for advanced packaging architectures. This study applied frontside delayering and backside thinning methods to a COTS device and captures the challenges encountered during these processes. Difficulties were observed in frontside delayering as a result of die bow, interface layer composition, and silicon support structures, whereas through-silicon vias (TSVs) were not observed to negatively impact overall frontside delayering quality. Challenges observed during backside thinning were a result of die bow, delamination, and interface layer composition, whereas TSVs in the interface were not observed to negatively impact backside thinning quality. The work done in this study showcases practical sample preparation challenges for hardware assurance of ICs in heterogenously integrated systems and how the community can begin to adapt conventional V&V methodologies for emerging technologies.