Non-Destructive Hardware Trojan Circuit Screening by Backside Near Infrared Imaging

Hardware Trojan detection is a critical topic for maintaining the security of IC supply chain. Previous studies have reported some HT detection methods by reverse engineering manufactured chips, extracting design data, and comparing it with golden design data that is verified to be free of HT. However, there is a problem in terms of inspection time because time-consuming, high-resolution methods such as scanning electron microscope (SEM) must be used to accurately extract the structure of submicron order ICs. Typically, the inspector does not know where the HT is placed on the chip, and it takes an unrealistic amount of time to scan the entire chip with SEM to reconstruct the design data. In addition, SEM inspection involves destructive processes such as delayering. The inspector must identify chips suspected of HT insertion before inspection. In this paper, we propose an HT detection flow with a screening process that identifies suspected HT-inserted chips and the location of HT insertion prior to a high-resolution imaging process such as SEM. The screening process observes transistor layers by near-infrared (NIR) imaging from the backside of the IC and quickly and non-destructively detects additional logic cells laid out from the HT trigger circuit insertion. Although NIR is not suitable for observing microstructures such as the bottom wire layers due to its optical limitation, its resolution is sufficient to detect large structural changes such as groups of multiple logic cells. In the experiment, backside NIR observation was performed on a TEG chip fabricated with a 180 nm process. We show that logic cells of a certain size, such as FFs, can be resolved by NIR imaging.