A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design

With the continuous shrinking of the size of the semiconductor process, the multi-node upset (MNU) brought about by the charge-sharing effect in the nano-integrated circuit has a huge impact on the reliability of the chip. In this paper, a low-delay quadruple-node-upset self-recoverable (LDQNUSR) latch is proposed, which employs seven identical multi-level soft-error interception modules (SIM), each of which is composed of six two-input C-element (CEs) and an inverter. Due to the error interception characteristics of each SIM and the mutual feedback mechanism, this latch has complete quadruple-node-upset (QNU) self-recovery capabilities. Simulation results show that the proposed latch can tolerate all QNUs and can self-recover from any QNUs. In addition, latch overhead can be reduced due to the use of high-speed transmission gates and clock gating techniques. The proposed latch has lower delay compared to the latest LDAVPM latch.