FPGA-Based Cross-Hardware MBU Emulation Platform for Layout-Level Digital VLSI

As the feature size of integrated circuits (ICs) continues to shrink, radiation-induced multiple bit upsets (MBUs) become more frequent than single bit upsets (SBUs) in nanometer ICs. However, it is still very difficult and time consuming to evaluate the sensitivity of digital very large scale ICs (VLSIs) to MBUs. To accelerate MBU evaluation, an MBU emulation platform is proposed via hardware-software co-design approach in this paper. Based on the proposed layout back-annotation technique, the platform back-annotates information of adjacent flip-flop (FF) cells in layout-level physical gate-level (PGL) netlist to the matching register cells in register transfer level (RTL) code, and is able to perform fast and accurate MBU emulation for layout-level digital VLSIs. Finally, several experiments on four different digital designs are implemented with Xilinx Zynq-7000 FPGA, and the correctness and effectiveness of the proposed MBU emulation platform are verified by these experiments.