A Biased Mixed-Precision Convolution Engine for Hardware-Efficient Computational Imaging CNN

Mixed-precision networks have demonstrated significant advantages in CNN acceleration for edge inference. They can achieve high throughput and energy efficiency while maintaining quality in resource-constrained environments. However, existing high-performance accelerators for bit-flexible computation suffer from significant hardware overheads due to the extra sign extension in bit-level decomposition, severely confining the performance enhancement in mixed-precision networks. In this paper, we aim to facilitate efficient inference for mixed-precision networks in computational imaging applications. First, we propose a biased multiplier to optimize hardware performance for bit-flexible architectures. Unlike the conventional bit-level decomposition, the proposed biased representation (BR) avoids sign extension to enhance hardware efficiency. On top of that, we build 4/8-bit biased mixed-precision networks and convolution engines with highly-parallel eCNN accelerator for evaluation. We implement convolution engines with three types of multipliers, uniform-precision, sign-extended, and biased multipliers, on TSMC 40 nm technology to support advanced super-resolution and denoising at 4K UHD 30fps, FHD 60fps and FHD 30fps. Compared to the sign-extended counterpart, synthesis results show that our biased mixed-precision convolution engine can provide area overhead and energy reduction by 50%. At the same level of image quality, it can also deliver 33% energy reduction on average over the uniform-precision method.