Robust Body Biased Level Shifter

As an integrated circuit, the system on a chip integrates a whole electronic system onto it. The various functional blocks inside the system on a chip may work at different voltage levels. In such multiple-V
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systems, reliable level shifter circuits are necessary for voltage conversion among the various functional blocks of the system on the chip to retain the overall functionality of the system. The proposed Robust Body Biased Level Shifter (RBBLS) uses an error correction circuit and a cut-off transistor to lower the contention and the static current. The RBBLS uses a bias voltage of 0.6 V with a supply voltage of 1.2 V. The circuit is implemented using Cadence Virtuoso at 45 nm technology with an input frequency ranging from 1 Hz to 1 MHz along with the upside voltage conversion range from 0V-0V and 120mV-1.2V. The RBBLS has a delay of 249.8 ns at a 0.01 MHz input pulse frequency (fIN), energy per unit transition of 1.52 pJ, power consumption is 15.22 nW and a power delay product of 3.801 fWsec. The RBBLS shows a drop in delay, power, energy and power delay product by 95.62%, 82.48%, 82.44%, and 99.23%, respectively, as compared with the re-implemented Robust Level Shifter from the literature.