Design and Implementation of a Strong Arbiter PUF for the Security of FPGA

Physical unclonable function (PUF) is a promising process for safe key generation on ICs and IoT devices for authentication and cryptographic applications. Each Physical Unclonable Function (PUF) stands apart due to tiny variations introduced during manufacturing, like minuscule gate delays. PUF provides responses when input challenges are given. One of the core advantages of Arbiter PUFs lies in their resilience against conventional attack methods like reverse engineering, side-channel attacks, and brute-force attempts. As the PUF’s distinctiveness and randomness stem from its physical structure, adversaries face formidable obstacles when attempting to simulate or forecast its behavior. Recently, researchers proved that some arbiter PUFs can be susceptible to modeling and Machine Learning (ML) Attacks. Researchers continue to explore countermeasures and improvements to enhance the security of Arbiter PUFs and other PUF variants. In our paper, utilizing a computer-aided (CAD) tool, a strong arbiter PUF (APUF) is designed and implemented on a Field Programmable Gate Array (FPGA). The challenges and responses of APUF are 64 bits, which makes it unpredictable and difficult to break using machine learning and deep learning algorithms. Our implemented APUF’s performance was evaluated based on inter and intra-hamming distance of responses. The arbiter PUF achieved 0.031% intra-hamming distance (HD
intra
) and 30% inter-hamming distance (HD
inter
), which are closely ideal.