VHDL Realization of a Hardware Accelerator for k-NN Classification

The machine learning has a very broad specter of application in modern world. One of the important roles of the machine learning is in process of classification. Since the classification is very computational heavy process, the hardware accelerator can alleviate the work of processor and improve the implementation of machine learning process. In this paper we present our hardware accelerator for the k-Nearest Neighbours (k-NN) classification. The results of the implementation on the FPGA confirm the functionality of this accelerator, and the results of the implementations for various values of the parameters show that the accelerator size isn’t affected significantly by them, so the parameters can be chosen according to the application demands.