A 0.636 mW 8-bit 90 kS/s SAR ADC in 130 nm CMOS Process

This paper presents the design of an 8-bit successive-approximation (SAR) analog-to-digital converter (ADC) using 130 nm UMC CMOS technology. The ADC contains a sample and hold circuit, a comparator, a serial D flip-flop based SAR and a digital-to-analog converter (DAC). A two-stage operation amplifier based comparator gives a simple ADC structure with very low power consumption. With a 1.2 V supply voltage and input signal frequency of 10.1 kHz, the sampling rate is 90 kS/s with 0.636 mW power consumption. The average integral non-linearity (INL) and differential non-linearity (DNL) are less than 1 LSB with effective number of bits (ENOB) of 7.52 bits and the signal to noise and distortion ratio (SNDR) of 47.01 dB.