Design of an Energy-Efficient SRAM Cell with Optimum Cell Ratio

The pre-charge, write enables, sense amplifier enables, read enables, and rows and columns encoders of SRAM cell are all considered in this paper. In SRAM memory cell, these components play different roles and are usually implemented as separate circuit blocks around the SRAM memory array. The 8T SRAM cell was built using the Tanner Tool on 45nm technology, which is an industry-standard tool. This tool helps in designing and simulating integrated circuits, including SRAM cells. To establish an efficient SRAM architecture, several semiconductor circuits are available. SRAM cells commonly use a four-transistor circuit in low-power VLSI applications. The 4T SRAM cell is a widely used design due to its balance between performance, area efficiency, and power consumption. To boost power efficiency at various ideal cell ratios, 8 transistors (8T) SRAM designs are employed instead of conventional circuits in this analysis. While designing an 8T SRAM circuitry incorporating write driver logics, power consumption is assessed including both static and dynamic conditions. This research involves the investigation of variable decay of power, which refers to the dynamic power consumption that varies based on the circuit activity and input patterns. Analysing and characterizing the dynamic power behaviour of SRAM cells under different operating conditions and workloads will be an important aspect of my research. Tanner's EDA tool suite is deployed for schematic entry and capture of the SRM cell. T-Spice based simulation is used to obtain the netlist, whereas, W- Edit is run to review the waveforms. The assessment of circuitry is carried out at the voltage of 1.1V. The purpose of this research is to create a design and compute all of the characteristics that contribute to the stability of an 8T Static RAM cell in 45nm technology, as well as the optimum cell ratio based on the measured parameters i.e. read noise margin (RSNM), hold noise margin (HSNM), read delay, and write delay.