Robust and Efficient Design of On-Chip Compact Delay Units Based on Bridged T-Coil

This paper presents a robust and efficient design methodology for on-chip compact delay units using the bridged T-coil (BTC). This layout design methodology reduces circuit complexity by realizing the BTC with a center-tapped return path close to the input and output ports. Further, coupled inductor designs with a rotationally adjustable inductor layout and a modified differential layout enable wider control of positive and negative magnetic coupling coefficient while keeping layouts compact. The new design methodology provides single-pass layout designs for delay units with BTCs. The design methodology is demonstrate in a Tower Semiconductor 0.18µm SiGe BiCMOS process with fullwave electromagnetic simulations for singled-ended and differential BTC designs with lowpass delay characteristics and cascaded BTCs with flat bandpass group and phase delay characteristics.