Simulation Research on Parasitic Parameter Extraction of LDO Power Chip Package Based on ANSYS Q3D

This paper introduces a parasitic parameter extraction method of low dropout regulator (LDO) power chip package based on ANSYS Q3D simulation technology. Firstly, according to the package size of LDO power chip, the paper uses ANSYS Q3D software to model the pin package and bonding line. Secondly, Q3D simulation software is used to extract the parasitic parameters of the pins and bonding of the LDO power chip. Finally, continuous wave (CW) electromagnetic interference (EMI) and periodic rectangular pulse wave are used as interference excitation to analyze the parasitic parameters of chip pins and EMI. The advantage of this method is that it uses commercial simulation software to simulate and extract parasitic parameters of the known package and bond structure of LDO power chip, and overcomes the difficulty of extracting package and bond line of LDO chip. This method has important reference value for extracting parasitic parameters of chip pin package.