FPGA Based Data Acquisition for DC Grids

This paper aims to explore the design of an FPGA-based 8-channel data-acquisition device. The hardware and hardware design language described in this paper, are purpose-built for a select set of components. These components are selected to guarantee a minimum data acquisition rate of 30 MS/s per channel. This paper will detail a general system overview and part selection, followed by the tested part of this system.