A D-Band High Efficiency Dual-Mode Power Amplifier Using Switching Adaptive Bias in 40-nm CMOS Technology

The paper presents a dual-mode high-efficiency power amplifier (PA) with a center frequency of 140 GHz. A switching adaptive bias circuit is used for the PA in order to adjust the gate voltage bias of the output stage by detecting the power at the output to improve the power added efficiency (PAE) and power back-off (PBO) Efficiency. In addition, switching between high power (HP) and low power (LP) modes can be performed by tuning the switch in the adaptive bias. The proposed PA achieves a P
sat
of 12.2 dBm and a peak PAE of 10.8% in HP mode, with a 3 dB-bandwidth of 22.5 GHz and a peak S
21
of 21.7 dB, while achieves a Psat of 9.8 dBm, a peak PAE of 9.5% and a peak S
21
of 16 dB in LP mode. The power consumption in the two modes is 131 mW and 65 mW, respectively. The PA is designed in 40nm CMOS technology with a core area of only 0.047 mm
²
.