An 18.6-dBm, 8-Way-Combined D-Band Power Amplifier with 21.6% PAE in 22-nm FD-SOI CMOS

This paper presents a 2-stage, 8-way power-combined fully depleted silicon-on-insulator (FDSOI) CMOS power amplifier (PA) operating from 110–125 GHz. An optimal power combining strategy realizes high power-added efficiency (PAE) with 8 pseudo-differential stages power cells matched approximately to 50 Ohms. Additionally, low-loss output matching networks improve PAE using sub-quarter wavelength (SQWL) coupled-line baluns (CLB). Fabricated in 22-nm FD-SOI CMOS technology, the PA generates 18.6-dBm saturated output power
$(P_{sat})$
, 21.6% peak PAE at 18.2-dBm, and occupies 0.183 mm 2 core area. The power density is 0.4 W/mm
²
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