Analysis of Area Efficient Parallel FIR Filters using FPGA

Finite Impulse Response (FIR) filters are known for their stability and the reason being widely used over Infinite Impulse Response (IIR) filters. Out of many FIR filters, parallel FIR filters are chosen the best over other filters in digital signal processing. This paper compares the design of a basic 3-parallel FIR filter as well as two versions of Area-Efficient 3-FIR filters. Booth’s algorithm and Carry-look-ahead adder are used as the basic components of this filter. The Area-Efficient filters are later compared after designing them. The simulation has been carried out using Xilinx ISE design suite 14.7. The FIR filters are later implemented on Spartan XC6SLX16-2FTG256 as the FPGA hardware.