Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node

The proposed circuit has several objectives, the most important of which is to increase speed while simultaneously reducing power consumption. We will use a number of techniques on the 6T SRAM cell in order to accomplish this objective. The objective is to reduce the amount of power that is wasted as a result of leakage while maintaining the same level of functionality that the cell now has. "Static random access memory" (SRAM) is a form of RAM that does not require regular data refreshment. This type of RAM is denoted by the acronym "SRAM." SRAM cells have been processed in various ways, all to reduce the amount of power lost due to leakage while maintaining their operational capabilities. Read, write, and hold are the three distinct modes of operation that are suggested by this investigation's gated PMOS 6T SRAM cell. The proposed design seeks to achieve some important objectives, the most important of which are to reduce leakage current in standby mode, increase stability in active mode, and retain the logic state when the hold mode is activated.