Design of Arithmetic Logic Unit Using Hybrid Power Reduction Methodologies For Super Computer Applications

Arithmetic logic unit (ALU) is used to perform mathematical and bitwise operation on integers that are combined in digital circuit used for supercomputing applications. Energy consumption has become a particularly critical issue as a result of the Internet of Things (IoT) device technology's quick development. The full adder circuits are used in the ALU structure mainly affects its power, area, and delay. In existing approach, the ALU circuits are implemented using fully swing gate diffuse input logic. In this article, the design of an ALU using hybrid VLSI methodologies has been proposed. Using the Cadence Virtuoso tool, the proposed and existing ALU is designed and tested on 180 nm CMOS technology. The proposed design and other circuit topologies that are mentioned in the literature will be contrasted in terms of delay efficiency, power reduction, and other assessment metrics showing circuit performances. Based on the results obtained the proposed design has better PDP without any performance degradation.