Ultra-Low Power Approximate Arithmetic Circuits

Multiplication and addition are the two paramount arithmetic operations in application specific ICs and DSP processors. The power consumption, area and performance are the major constraints in scaled CMOS integrated circuits. The computation using accurate computing techniques includes overhead in terms of area and time. The accurate computation is not the constraint for data mining, big data, AI, Internet of Things, deep learning applications. In such cases, it would be more viable and cost-effective if computing is done with the results are properly accurate is called approximate computing. So, a 4-bit approximate adder and multiplier circuits are implemented in this work using energy recovery logic at 45nm technology node using cadence virtuoso. Eldo simulator is used to perform functional verification. The combined use of energy recovery logic with approximate computing achieves about 50-75% power reduction over corresponding CMOS implementations. Further, analyzed the behavior of these circuits with supply voltage scaling and technology by varying the amplitude of power clock from 0.4V-1.8V and width of the transistor from 120nm-160nm. Along with this analysis another prominent design metric in SoC applications is Area Power Product (APP), which is also computed in this work