Design of Dynamic comparator using CMOS and FINFET technologies

A two-stage and three-stage dynamic comparator architecture is proposed using FINFET technology for high speed, low power dissipation and comparison is done between three-stage and two-stage dynamic comparators with and without tail transistors. The designed comparator compares the two analog input voltage signals and generates the greater signal as the output. FINFET technology is used to overcome the short-channel effects in CMOS. In this paper the FINFET is designed with different supply voltages and analyzed power dissipation and delay. The comparison with tail and without tail of two-stage and three-stage comparators specifies that the delay and power dissipation has been reduced greatly with tail transistor. Two-stage, Three-stage Dynamic Comparator are designed and simulated in HSPICE using 16nm and 20nm CMOS and FINFET technologies.