Advanced Powerplanning Strategy Utilising Aprisa - Image Edge Detector

A good powerplanning is a must to provide power to every macro, standard cell and other cells in the design.With the advancement in technology and the chip sizes reducing day by day we need faster RTL to GDS flow for the design of a chip , so powerplanning being a part of this stage should not take major part of time in the full flow design so we need to switch to automated approach of powerplanning rather than a Conventional one (which is time consuming as the chip sizes get smaller and smaller).A good powerplanning and that also done in less time has great benefits in the routing stage for the design.The design of an Image Edge Detector is done using the library and liberty files of 90 nm technology node. In a Conventional power ground (PG) script various parameter challenges are to be faced and in order to find them ,it is a hectic task. Thus to overcome this challenge of runtime and complexity issues related with the Conventional PG scripting,we have come up with the Auto power ground (PG) script approach. In this approach we write a script which focuses on just 4 parameters i.e width,group step,siblings number and siblings step majorly for the powerplanning of the design.We find the DRCs related with the design using Conventional PG is 5.9 lakhs compared to the count of just 148 for Auto PG. Whereas the IR drop for VDD is 1.44% for Conventional PG and 1.27% for Auto PG, also for Ground net the IR bounce is 4.18% for Conventional PG and 3.75% for Auto PG.