Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology

Performing an investigation on the power consumption and delay parameters of 6T and 9T SRAM cells, respectively. Memory power consumption is a crucial design aspect because of the direct impact it has on the overall energy efficiency of the system as well as the amount of power that it draws. Because it requires a larger voltage swing during write operations and is more vulnerable to leakage currents, the 6T SRAM cell is often the one that consumes more power than its 9T counterpart. On the other hand, the 9T SRAM cell has a differential write mechanism that helps decrease the voltage swings and leakage currents, which results in less energy being used by the cell. The amount of time that must pass before a memory cell may be read from or written to is referred to as the "access time." Because of its more straightforward design and more compact transistors, the 6T SRAM cell often demonstrates faster access times than its 9T SRAM counterpart. The increased number of transistors in the 9T SRAM cell causes an increase in the access latency experienced by the cell. As can be observed from the comparison of performance, the power and delay characteristics of 6T and 9T SRAM cells are distinct from one another. The 9T SRAM cell consumes less power but has much longer access times than its 6T cousin, which normally draws more current but offers faster read/write operations. These differences are due to the fact that the 9T SRAM cell has a higher density of transistors. With the assistance of the Tanner software, the 6t and 9t SRAM topologies have been included into the 7nm predictive technology model (PTM).