System-on-Chip Design for Fast Ultrasonic Chirplet Signal Decomposition Algorithm

Decomposition and characterization of backscattered ultrasonic multiple interfering echoes is a critical step for analyzing the ultrasonic propagation path, propagation modes, coupling condition of the transducers and detecting defects within the propagation path. Chirplet Signal Decomposition (CSD) is an efficient way of analyzing ultrasonic echoes. However, CSD is computationally expensive and time-consuming for real-time signal processing applications. To address this problem, we present a System-on-Chip (SoC) implementation of the CSD algorithm, with the goal of speed optimization and real-time execution without sacrificing the accuracy of the signal decomposition and reconstruction. The implementation was tested on a Zynq Ultrascale+ series FPGA and achieved an echo estimation within two milliseconds.