High-level FPGA Design of Deep Learning Hyperspectral Anomaly Detection

Hyperspectral image Anomaly Detection (HSI-AD) has attracted considerable attention in the field of remote sensing. With improved detection accuracy, as a consequence of the increasing complexity of HSI-AD algorithms, more computing resources are required. In this paper, a hardware implementation utilising High-Level Synthesis (HLS) of Deep Belief Network (DBN) anomaly detector is proposed. The original sequential implementation is adapted into HLS through Vitis software and design optimisation to use on-chip memory for network weights and biases towards increased throughput are proposed. The addition of on-chip memory in the proposed design achieved a 72% reduction in time for performing auto-encoding and reconstruction error calculation compared to software.