A Machine Learning-Based Post-Route PVT-Aware Power Prediction of Benchmark Circuits at Floorplan Stage of Physical Design

This paper is devoted to the study of the application of machine learning (ML) algorithms for power prediction at floorplan stage of physical design of integrated circuits (ICs). Reduction of the power consumption can lead to additional iterations in the design flow since a realistic calculation of power is possible at the final stages. Unlike the existing works, the proposed method considers the variations of process, supply voltage, temperature, threshold voltage, frequency, and floorplan related parameters. For estimation of the proposed method, the circuits from IWLS05 benchmark and 8 ML algorithms were used. The mean absolute percentage error is approximately 13% for unseen designs with mentioned parameters' variations. The disadvantage of the method is the necessity to go through the full design flow of the selected designs with a selected range of parameters to collect data necessary for training ML models, which requires additional machine and time resources.