Titan 2.0: Enabling Open-Source CAD Evaluation with a Modern Architecture Capture

This paper presents an updated version of the Titan (Quartus + VPR) flow, and a VPR-compatible architecture description of Intel's Stratix 10 device. Together these components enable large designs to be targeted at a complex and realistic architecture, facilitating improved benchmarking and optimization of open-source CAD flows. Additionally, the Stratix 10 architecture capture is a useful baseline architecture on which proposed new FPGA features can be evaluated. We capture the device primitives, intra-block connectivity, device floorplans, routing architecture and timing with reasonable fidelity in the human-readable VTR architecture format, enabling easy modification by researchers. Using the updated Titan flow and Stratix 10 capture, we compare the quality of results (QoR), runtime, and resource utilization of VPR to Quartus Prime. The results show that VPR's overall runtime is comparable and its memory footprint is smaller than that of Quartus, but the packer runtime is higher and Quartus achieves better wirelength and frequency. We identify causes of the slower packing runtime in VPR and suggest directions for future improvements.