Performance Analysis of Strain Channel High-K Gate Stack Gate Underlap Cylindrical GAA FET

In this work, a Strained channel High-K Gate Stack Cylindrical Gate All Around FET (SC-HK-GS-CGAA FET) with gate underlap has been proposed and analyzed to provide greater switching speed with a smaller subthreshold swing. It has been accomplished by improving on-current using high-K gate stacks, which increase fringing field capacitance, resulting in increased carrier concentration and strained technology on channel, boosting carrier flow by quasi-ballistic transport, and confinement of carrier. Furthermore, the suggested device's off-current is reduced by using gate-source/drain underlap. The ultra-thin strain is made up of a cylinder-shaped outer s-Si layer that surrounds the central s-SiGe layer and forms a quantum well between them. This improves the Ion/Ioff ratio and achieves better subthreshold swing for SCEs while also increasing current density and decreasing leakage current. The results show that the 8nm high-k gate stack strained channel CGAA FET amazed 251
^%
enhancement of Ion/Ioff ratio over the 22nm High-K CGAA FET and 74.61% reduction of leakage current over the 22nm High-K CGAA FET. All these improvements warrant HK-GS-SC-CGAA FET as best suited device for high-speed switching device in digital application.