The Fastest CMOS Single-Channel 5-bit Flash ADC Operating at 18.5 GS/s in 22 nm FD-SOI

This paper presents the design and implementation of a 5-bit $18.5 \mathrm{GS} / \mathrm{s}$ flash ADC. The focus of the work has been on the single-channel implementation of the ADC at the target speed to avoid extra complexity and effort introduced by time-interleaved converters. This flash ADC according to our best knowledge is the fastest single-core 5-bit flash ever realized in CMOS technology. Utilization of a two-stage latch design along with forward-body-biasing (FBB) are the key points to achieve the required comparator speed. Furthermore, employing a novel body-biased preamplifier to generate the flash references, the power-hungry low-ohmic R-ladder and the classical differential difference amplifier (DDA) are eliminated saving huge power as well as reducing the kickback noise. The SF-based T&H core operates from a $1.2 \mathrm{~V}$ supply consuming $67 \mathrm{~mW}$. The rest of the core blocks including clock-trees use a $0.9 \mathrm{~V}$ supply and consume $200 \mathrm{~mW}$. Characterization results reveal a Nyquist SFDR and SNDR of 33.6dBc and $25 \mathrm{~dB}$ (ENOB=3.9 bits) respectively using a full-scale single-tone sine wave input $\left(f_{\text {in }}=9.1 \mathrm{GHz}\right.$). The LF SFDR and SNDR are 35.2dBc and $28 \mathrm{~dB}$ (ENOB=4.3 bits) respectively $\left(f_{\text {in }}=4.7 \mathrm{MHz}\right.$). The core $A D C$ with pads occupies an area of $1.01 \mathrm{~mm}^{2}$, while the active area is $0.06 \mathrm{~mm}^{2}$.