Asynchronous HW-Implementation of IEC 61499

The IEC 61499 standard facilitates the deployment of flexible decentralized control architectures. Current IEC 61499 runtime systems nearly exclusively focus on synchronous software solutions. Although synchronous FPGA-implemented Function Blocks provide a speed-up, a single clock domain, which has been used so far, lowers the flexibility of individual Function Blocks. The event-based communication layout in the standard seems to lend itself rather to an asynchronous implementation. Consequently, this paper proposes an FPGA implementation in which the Function Blocks are internally still comprised of a (locally) synchronous state machine, while their communication follows asynchronous principles. We explore the feasibility of that approach by designing a comprehensive generic communication infrastructure and, on top of that, implementing a case study exhibiting randomized input variables and different clock and input frequencies in an FPGA. Based on this implementation, we explore the bottlenecks of our approach and elaborate potential improvements.