BAG2 Assisted Hierarchical Analog Layout Synthesis for Planar Technologies

Analog circuit design automation remains an intense area of attention and has seen both new and existing tools continued to be developed targeting different phases of the analog design flow to reduce development time and cost. One of the promising tools is the Berkeley analog generator (BAG2) framework which is an open-source analog layout generator for automating and verifying circuit layouts. It promises a process-independent flow as well as encourages design re-use due to using parameterized generators which can be scaled as required and this reduces the layout-development time compared to manual hand-made layouts. This work describes the effort and results of evaluating the BAG2 framework for the TSMC 65nm and Cadence GPDK 45nm processes. A case study is made with a number of circuits to discuss the problems in setting up and using BAG2 for the above technologies as well as the limitations and solutions required to utilize the framework effectively.