Path Margin Monitor for Silicon Lifecycle

As size and complexity of SOC continue to increase, the requirement for product performance and longevity has also become vital part of chip designing. By deploying monitors and structures embedded within silicon design we can get real time data about the performance of chip which in-turn can be used to study the health of the silicon and in predicting the degradation of silicon. Analysis of the data can also be used for failure avoidance and deploying preventive measures to improve the longevity of the silicon. Currently Ring oscillators and other Process, Voltage, Temperature sensors are widely used to measure various parameters of silicon in infield, however their accuracy scope and usage are limited. Monitoring the actual functional paths in silicon will provide more accurate functioning of the chip. In this paper we present Path Margin Monitor which can monitor the functional paths of silicon in real time through complete silicon lifecycle. Path Margin Monitor provides in-situ monitoring of signal paths in ASIC designs that are either timing critical, have high impact on system performance or are at risk of higher degradation due to aging through the lifecycle of chip. The data collected by Path Margin Monitor will be useful for silicon lifecycle management - diagnose the health of silicon, predict failures, and take preventive measures to improve the lifecycle of chip.