A Divide-by-16 CML Frequency Divider for K-Band Radar Applications

In this paper, we present a current mode logic (CML) divide-by-16 frequency divider designed using a 110 nm technology node. The circuit is constructed from four CML divide-by-2 frequency dividers and a buffer stage for outputting square wave signals. The buffer stage is used to drive true single-phase-clock (TSPC) programmable frequency divider. The simulation results show a locking range of 20 GHz, from 8 GHz to 28 GHz. The power consumption of the circuit at DC is 16.6 mW, and the core area of the divider is only 0.022 mm
²
.