Study on Spurious Suppression Behavior of Fractional-N and DDS Based PLL Synthesizers with Fine Frequency Resolution

A comparison study on spurious suppression behavior of fractional-N and direct digital synthesizer (DDS) based phase-locked loop (PLL) Synthesizers is reported in this paper. It is well-known that a fractional-N synthesizer with delta-sigma modulator (DSM) suffers serious problem of integer boundary spurious and fractional spurious. A hybrid scheme of DDS and integer-division PLL is an effective way to alleviate this problem in the development of frequency sweeping synthesizers with high frequency resolution. To quantitatively evaluate the improvement of the spurious suppression of the DDS based PLL to fractional-N synthesizer, a comparison study of the two schemes of the frequency synthesizers has been carried. ADI’s HMC778 was adopted to generate form the fractional-N PLL, by adjusting the frequency ratio of the fractional divider in the chip, a fine-resolution sweeping frequency source working in X-band was implemented. A hybrid frequency synthesizer scheme, where HMC778’s internal VCO is combined with ADI’s DDS AD9910 as the reference source to the integer frequency division PLL, is adopted. In this way, the expected signal with ultra-fine frequency step size can be delivered from the DDS and multiplied by the fixed integer frequency division ratio to the same frequencies of the fractional-N PLL. The two frequency synthesizers are measured and compared in regard to spurious suppression behavior. The fabricated hybrid frequency synthesizer avoids the integer boundary spurious and fractional spurious caused by fractional frequency ratio, which basically has 39dB better integer boundary spurious suppression at the frequency from 9.9 to 10.7GHz. Simultaneously, it is observed that the noise floor is improved by 5dB in 200KHz bandwidth. The results of this work are valuable to balance system complexity and spurious suppression requirement in practical applications.