A 232GHz Frequency Multiplier Chain(×4) in 65-nm CMOS with Harmonic Rejection Ratio of 40dBc

A 232GHz frequency multiplier chain(×4) in 65-nm CMOS technology is demonstrated. The design includes two balanced frequency doublers and two driving amplifier(DA). In order to obtain good differential input signal, slot-balun is used between the first-stage and second-stage frequency doubler, and the amplitude error and the phase error of slot-balun are within 0.05dB and 0.15° respectively. The 3dB bandwidth of the multiplier is 220GHz~244GHz (about 10%), the peak conversion gain(CG) is -10dB at 232GHz, and the harmonic rejection ratio is higher than 40dBc.The frequency multiplier consums 28.4mW DC power, and the size of the chip is 950um×460um.